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PRELIMINARY W986432DH 512K x 4 BANKS x 32 BITS SDRAM
GENERAL DESCRIPTION
W986432DH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 512K words x 4 banks x 32 bits. Using pipelined architecture and 0.175 m process technology, W986432DH delivers a data bandwidth of up to 800M bytes per second (5). For different application, W986432DH is sorted into four speed grades: -5, -55, -6, -7,-8. Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time. By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W986432DH is ideal for main memory in high performance applications.
FEATURES
* * * * * * * * * * * * *
3.3V 0.3V power supply 524288 words x 4 banks x 32 bits organization Auto Refresh and Self Refresh CAS latency: 2 and 3 Burst Length: 1, 2, 4, 8, and full page Sequential and Interleave burst Burst read, single write operation Byte data controlled by DQM Power-down Mode Auto-precharge and controlled precharge 4K refresh cycles/64 mS Interface: LVTTL Packaged in 86-pin TSOP II, 400 mil - 0.50
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Publication Release Date: May 2000 Revision A0
PRELIMINARY W986432DH 512K x 4 BANKS x 32 BITS SDRAM
PIN CONFIGURATION
DQM1 DQM3 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 45 42 DQ23 VCCQ VCCQ VCCQ VCCQ VSSQ VSSQ VSSQ VSSQ
DQ9
DQ8
CKE
CLK
VSS
VSS
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
A10/AP
VSSQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQM0
DQM2
VCCQ
VCCQ
DQ22
CAS
RAS
BS0
VCC
VCC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
BS1
WE
NC
CS
NC
VSSQ
NC
A0
A1
A2
VSSQ
VSSQ
VCCQ
VCC
PIN DESCRIPTION
PIN NAME A0-A10 FUNCTION Address DESCRIPTION Multiplexed pins for row and column address. Row address: A0-A10. Column address: A0-A7. A10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by BS0, BS1. BS0, BS1 DQ0-DQ31
CS
Bank Select Data Input/ Output Chip Select
Select bank to activate during row address latch time, or bank to read/write during address latch time. Multiplexed pins for data output and input. Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Command input. When sampled at the rising edge of the clock RAS , CAS and WE define the operation to be executed. Referred to RAS Referred to RAS
RAS
Row Address Strobe Column Address Strobe Write Enable
CAS WE
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Publication Release Date: May 2000 Revision A0
VCCQ
VCC
43
2
3
4
5
6
7
8
1
9
44
VSS
NC
NC
NC
NC
Vss
A9
A8
A7
A6
A5
A4
A3
W986432DH
DQM0- DQM3 CLK CKE Input/output mask The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. Clock Inputs Clock Enable System clock used to sample inputs on the rising edge of clock. CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. Power for input buffers and logic circuit inside DRAM. Ground for input buffers and logic circuit inside DRAM.
VCC VSS VCCQ VSSQ NC
Power (+3.3V) Ground
Power (+3.3V) for Separated power from VCC, to improve DQ noise immunity. I/O buffer Ground for I/O buffer No Connection Separated ground from VSS, to improve DQ noise immunity. No connection
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Publication Release Date: May 2000 Revision A0
W986432DH
BLOCK DIAGRAM
CLK CLOCK BUFFER CKE
CONTROL
CS
SIGNAL
RAS CAS
GENERATOR
COMMAND
DECODER WE ROW DECODER COLUMN DECODER COLUMN DECODER ROW DECODER
A10
CELL ARRAY BANK #0
CELL ARRAY BANK #1
A0 ADDRESS BUFFER
MODE REGISTER
SENSE AMPLIFIER
SENSE AMPLIFIER
A9 BS0 BS1
DATA CONTROL CIRCUIT COLUMN COUNTER
DQ BUFFER
DQ0 DQ31
REFRESH COUNTER
DQM0~3
COLUMN DECODER ROW DECODER ROW DECODER
COLUMN DECODER
CELL ARRAY BANK #2
CELL ARRAY BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE: The cell array configuration is 2048 * 256 * 32
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W986432DH
DC CHARACTERISTICS
Absolute Maximum Rating
PARAMETER Input, Column Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current SYM. VIN, VOUT VCC, VCCQ TOPR TSTG TSOLDER PD IOUT RATING -0.3 - VCC +0.3 -0.3 - 4.6 0 - 70 -55 - 150 260 1 50 UNIT V V C C C W mA NOTES 1 1 1 1 1 1 1
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0 to 70C)
PARAMETER Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input High Voltage Input Low Voltage
SYM. VCC VCCQ VIH VIL
MIN. 3.0 3.0 2.0 -0.3
TYP. 3.3 3.3 -
MAX. 3.6 3.6 VCC +0.3 0.8
UNIT V V V V
NOTE S 2 2 2 2
Note: VIH (max.) = VCC/VCCQ+1.2V for pulse width < 5 nS VIL (min.) = VSS/VSSQ-1.2V for pulse width < 5 nS
CAPACITANCE
(VDD = 3.3V, TA = 25 C, f = 1 MHz)
PARAMETER Input Capacitance (A0 to A11, BS0, BS1,
CS
SYM. Ci
MIN. 2.5
MAX. 4
UNIT pf
,
RAS , CAS , WE ,
DQM, CKE) CCLK Co 2.5 4 4 6.5 pf pf
Input Capacitance (CLK) Input/Output capacitance (DQ0-DQ31)
Note: These parameters are periodically sampled and not 100% tested
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Publication Release Date: May 2000 Revision A0
W986432DH
DC CHARACTERISTICS
(VCC = 3.3V 0.3V, TA = 0~70C) PARAMETER SYM. -5 MAX. Operating Current tCK = min., tRC = min. Active precharge command cycling without burst operation Standby Current tCK = min., CS = VIH VIH/L = VIH (min.)/VIL (max.) Bank: inactive state CKE = VIL (Power Down mode) CKE = VIH ICC2P TBD TBD TBD TBD TBD 3 CKE = VIH ICC2 TBD TBD TBD TBD TBD 3 1 bank operation ICC1 TBD -55 MAX. TBD -6 MAX. TBD -7 MAX. TBD -8 MAX. TBD 3 UNIT NOTES
Standby Current CLK = VIL, CS = VIH VIH/L=VIH (min.)/VIL (max.) BANK: inactive state
ICC2S
TBD
TBD
TBD
TBD
TBD
CKE = VIL (Power Down mode) CKE = VIH
ICC2P
S
TBD
TBD
TBD
TBD
TBD
mA
No Operating Current tCK = min., CS = VIH (min.) BANK: active state (4 banks)
ICC3
TBD
TBD
TBD
TBD
TBD
CKE = VIL (Power Down mode) (tCK = min.)
ICC3P
TBD
TBD
TBD
TBD
TBD
Burst Operating Current Read/Write command cycling Auto Refresh Current Auto refresh command cycling Self Refresh Current Self refresh mode
ICC4
TBD
TBD
TBD
TBD
TBD
3, 4
(tCK = min.)
ICC5
TBD
TBD
TBD
TBD
TBD
3
(CKE = 0.2V)
ICC6
TBD
TBD
TBD
TBD
TBD
PARAMETER Input Leakage Current (0V VIN VCC, all other pins not under test = 0V) Output Leakage Current 7(Output disable, 0V VOUT VCCQ) LVTTL Output H Level Voltage (IOUT = -2 mA) LVTTL Output "L Level Voltage (IOUT = 2 mA)
SYMBOL II(L)
MIN. -5
MAX. 5
UNIT A
NOTES
VO(L)
-5
5
A
VOH
2.4
-
V
VOL
-
0.4
V
-6-
W986432DH
AC CHARACTERISTICS
(VCC = 3.3V 0.3V, VSS = 0V, Ta = 0 to 70 C) (Notes: 5, 6.) PARAMETER Symbol MIN Ref/Active to Ref/Active Command Period tRC Active to precharge Command Period tRAS Active to Read/Write Command Delay Time tRCD Read/Write(a) to Read/Write(b)Command tCCD Period Precharge to Active(b) Command Period Active(a) to Active(b) Command Period Write Recovery Time CLK Cycle Time CLK High Level CLK Low Level Access Time from CLK Output Data Hold Time Output Data High Impedance Time Output Data Low Impedance Time Power Down Mode Entry Time Transition Time of CLK (Rise and Fall) Data-in-Set-up Time Data-in Hold Time Address Set-up Time Address Hold Time CKE Set-up Time CKE Hold Time Command Set-up Time Command Hold Time Refresh Time Mode Register Set Cycle Time CL* = 3 tOH tHZ tLZ tSB tT tDS tDH tAS tAH tCKS tCKH tCMS tCMH tREF tRSC 10 2.75 2.75 0 0 0.5 1 0.5 1.3 0.8 1.3 0.8 1 0.5 64 10.8 5 10 5 CL* = 2 CL* = 3 CL* = 2 CL* = 3 tCH tCL CL* = 2 tAC tCK tRP tRRD tWR 54 40 14 1 14 10 7 5 7 5 2 2 4.5 4.5 2.75 2.75 0 0 0.5 1.5 0.5 1.5 1 1.5 1 1.5 0.5 64 12 5.4 10 5.4 1000 1000 100000 -5 MAX MIN 55 40 15 1 15 10.8 7.5 5.4 7.5 5.4 2 2 5.5 5 2.75 2.75 0 0 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 64 ms ns 6 10 6 1000 1000 100000 -55 MAX MIN 60 42 18 1 18 12 7.5 6 7.5 6 2 2 5.5 5 1000 1000 Cycle ns 100000 -6 MAX ns UNIT NOTE
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Publication Release Date: May 2000 Revision A0
W986432DH
AC CHARACTERISTICS
(VCC = 3.3V 0.3V, VSS = 0V, Ta = 0 to 70 C) (Notes: 5, 6.) PARAMETER Ref/Active to Ref/Active Command Period Active to precharge Command Period Read/Write(a) to Read/Write(b)Command Period Precharge to Active(b) Command Period Active(a) to Active(b) Command Period Write Recovery Time CLK Cycle Time CLK High Level CLK Low Level Access Time from CLK Output Data Hold Time Output Data High Impedance Time Output Data Low Impedance Time Power Down Mode Entry Time Transition Time of CLK (Rise and Fall) Data-in-Set-up Time Data-in Hold Time Address Set-up Time Address Hold Time CKE Set-up Time CKE Hold Time Command Set-up Time Command Hold Time Refresh Time Mode Register Set Cycle Time CL* = 2 CL* = 3 tOH tHZ tLZ tSB tT tDS tDH tAS tAH tCKS tCKH tCMS tCMH tREF tRSC 14 3 3 0 0 0.5 0.5 1 0.5 1 0.5 1 0.5 1 64 16 7 10 7 CL* = 2 CL* = 3 CL* = 2 CL* = 3 tCH tCL tAC tCK Symbol MIN tRC tRAS tCCD tRP tRRD tWR 65 45 20 1 20 14 7.5 7 7.5 7 2 2 5.5 5 3 3 0 0 0.5 2 1 2 1 2 1 2 1 64 ms ns 8 10 8 1000 1000 100000 -7 MAX MIN 68 48 20 1 20 20 10 8 10 8 3 3 6 6 1000 1000 Cycle ns 100000 -8 MAX MIN MAX ns UNIT NOTE
Active to Read/Write Command Delay Time tRCD
-8-
W986432DH
PACKAGE DIMENSIONS
86L TSOP (II)-400 mil
86
44
E
HE
1 e b
43
C D
q
L A2 ZD A1 A L1
Y
SEATING PLANE
Controlling Dimension: Millimeters
DIMENSION (MM)
SYM.
DIMENSION (INCH) MAX.
1.20 0.15
MIN. A
A1 A2 b c D E HE e L L1 Y ZD 0.40 0.05
NOM.
MIN.
0.002
NOM.
MAX.
0.047 0.006
1.00 0.17 0.12 22.12 10.06 11.56 22.22 10.16 11.76 0.50 0.50 0.80 0.10 0.61 0.60 0.016 0.27 0.21 22.62 10.26 11.96 0.007 0.005 0.871 0.396 0.455
0.039 0.011 0.008 0.875 0.400 0.463 0.020 0.020 0.032 0.004 0.024 0.024 0.905 0.404 0.471
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Publication Release Date: May 2000 Revision A0
W986432DH
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
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